Demands for increased performance and complexity for integrated circuits have led to circuits including both CMOS transistors for high packing density and bipolar transistors for high power and speed. Such BiCMOS circuits provide particular advantages for mixed mode (analog plus digital) applications which can combine the low noise characteristics of bipolar transistors in analog subcircuits and still use well known CMOS digital subcircuits. See for example, R. Haken et al, "BiCMOS Processes for Digital and Analog Devices," Semiconductor International 96 (June 1989).
However, analog circuits typically will operate with both positive and negative power supplies and at higher voltages than the typical positive power supply digital circuit. For example, digital CMOS circuits typically operate between 0 and +5 volts, whereas analog circuits may operate with both -5 volt and +5 volt power supplies in addition to ground. Further, analog circuits benefit from the use of both CMOS transistors and bipolar transistors; thus a mixed mode BiCMOS circuit may have CMOS transistors operating between 0 and +5 volts plus other CMOS transistors operating between -5 and +5 volts. This complicates fabrication because the digital CMOS transistors will use a thinner gate oxide than the analog CMOS transistors in order to achieve sufficient performance. But then electrostatic discharge (ESD) protection becomes difficult.
Generally, MOS IC products are prone to ESD damage if their input and output pins were left unprotected, especially during handling. It is, therefore, a common practice to place ESD protection devices between the input or output pins and the supply voltage rails. MOS diodes as the ESD protection devices are used in a typical CMOS digital IC where the output signal swings between Vdd (+5.0 V) and Gnd (0 V). Usually, the silicon substrate is tied to Gnd, which makes the substrate to be the natural return point to both the output signal and the ESD current.
In mixed mode analog-digital system applications, it is very common to have blocks of circuit operating in several different voltage supply rails. For example, a digital circuit based on positive logic level would operate between Vcc (+5 V) and Gnd (0 V), while another digital circuit based on unusual negative logic level may operate between Gnd and Vee (-5 V). And analog circuitry may operate between Vcc and Vee. It is rather common for a BICMOS IC to have analog circuits at one end that operate between the full supply rails (Vcc and Vee) and digital circuits at another end operating between full supply rails, or the positive supply rails (Vcc and Gnd) for the positive logic compatibility. In this latter case, all digital signals would return to the Gnd supply and therefore the ESD protection for the signal pins would be implemented conventionally as shown by ESD protection devices 102 and 103 in FIG. 1a.
Typically the ESD protection devices are diodes such as Vceo diodes or Vebo diodes for bipolar circuits and NMOS or PMOS diodes or Zener diodes (if available) for CMOS circuits. ESD energy dissipates through the diode by avalanche breakdown or punchthrough, thereby creating a low impedance path.
It may not be necessary in many cases to place any ESD protection devices in between the signal terminal and the Vee supply rail because it is not relevant to the operation of the circuit under consideration, especially when gate oxides are relatively thick (greater than 250 .ANG.). Notice, however, that the return path for the ESD current is not necessarily the Gnd supply line in this case, because the silicon substrate is now tied to the Vee rail, not the Gnd line, as in MOS. Therefore, the conventional ESD protection scheme may be vulnerable to the ESD events when the discharge current path finds its way to the silicon substrate, especially for thin gate oxide devices. Thus the preferred embodiments include ESD protection device 105.
In high-performance, high-speed, mixed-mode BICMOS IC products, the digital circuits require thin gate CMOS devices and the bipolar devices need to have small outlines, both of which exacerbate the aforementioned ESD vulnerability even when the standard diode protection devices are implemented. The gate oxide of MOS devices or bipolar devices often fail when an ESD strikes the input or output or the power supplies due to the protection diodes having a too-high breakdown voltage or a too-slow response.
The actual ESD devices need to be nonlinear devices which present very high impedance to the circuit under normal circuit operation but quickly turn on into a very low impedance mode when the signal terminal reaches a certain threshold above the normal operating voltage. The ESD capture threshold of the ESD device should be set in such a way that it is higher than the normal supply rail voltages but sufficiently lower than the gate rupture voltage of the CMOS devices in the BICMOS digital circuit. Also, the substrate area occupied by the ESD devices should be small.
In BiCMOS processes the photomask count is typically high, and increasing the number of photomasks to obtain additional devices is only used as a last resort. Thus for a BiCMOS process there is a need to provide ESD protection devices fabricated from the process steps and which provide better ESD protection than the known diodes.
The present invention provides NMOS and PMOS devices with a Zener region formed in the drain to assist in NMOS and PMOS diode breakdown and thereby provide ESD protection. Such ESD protection devices are formed with the preexisting steps of a BiCMOS process.